Vælg din region

Vælg den region, der bedst passer til din placering eller dine præferencer.

Vælg dit webstedssprog

Denne indstilling styrer sproget for brugergrænsefladen, inklusive knapper, menuer og al tekst på webstedet. Vælg dit foretrukne sprog for den bedste browsingoplevelse.

Vælg sprog for jobannoncer

Vælg de sprog for jobannoncer, du vil se. Denne indstilling afgør, hvilke jobannoncer der vises for dig.

DTCO Layout R&D Engineer
imec

DTCO Layout R&D Engineer

Uspecificeret
Gem job

State-of-the-art DTCO research position for pathfinding near-future advanced CMOS technologies, working at the intersection of technology definition, layout, and circuit design.

What you will do

As CMOS scaling advances, the holistic co-optimization of technology and design for circuits and systems is more than ever essential to maintain performance increase together with power/area reduction in next generation chips. In our team, we focus on implications of near-future CMOS devices (e.g. nanosheet, CFET, 2D FET, etc.) at device, standard cell library, SRAM (i.e. bit-cell, macro) and block levels (e.g. processor, NoC, 3D). We do pathfinding for future technology enablers by Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) cycles. 

In this position, you will be involved in research & development of technology integrated design of logic and/or SRAM at advanced CMOS technology nodes beyond 2nm node. Based on imec's DTCO framework, you will interact with process and lithography engineering teams to define design rules, then you will custom layout, do physical verification (DRC, LVS), parasitic extraction (PEX) and characterize standard cell libraries, SRAM bit-cells/macros. You will analyze trade-offs between process and design requirements to achieve an optimal DTCO driven solution for different technology nodes. You will communicate to colleagues from device/BEOL stack modelling, block-level architecture, synthesis and physical design research. You will translate and propagate the device level technology choices to logic and/or SRAM level and will enable block-level PnR research. You will be responsible for DTCO of standard cell libraries and/or SRAM libraries, and improvement of characterization flows. You will also interact with system level designers to ensure a smooth power-performance-area and cost evaluation to assess the technology from process capabilities, up to digital system requirements.  

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. 

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits. 

Who you are

  • You have a PhD in Electronics or Electrical engineering, or relevant field, or a master’s degree with at least 5 years relevant industrial experience in CMOS design. 
  • You understand advanced semiconductor fabrication processes and devices. 
  • You have an excellent understanding of logic and SRAM design rules, layout and characterization in advanced CMOS technologies. 
  • Experience and good understanding of RTL design (e.g. VHDL, SystemVerilog), circuit-level digital logic design, synthesis (e.g. for ASIC or FPGA, Design Compiler, Genus, Vivado), static timing analysis, DRC-LVS decks, scripting and flow automation (e.g. tcl, shell, Python), PDK development and QA testing. 
  • Experience with commercial EDA tools for simulation (e.g. Spice, Spectre), schematic-layout design (e.g. Virtuoso, Custom Compiler), DRC-LVS physical verification (e.g. Calibre, IC Validator), parasitic extraction (e.g. Calibre, Raphael, StarRC, Quantus), logic library and/or SRAM characterization (e.g. Liberate) 
  • You are detail-oriented, organized and taking ownership of tasks but are also comfortable in critical thinking and making decisions to navigate the changing R&D demands. 
  • You are a capable coder that utilizes the power of versioning and documentation. 
  • You care deeply about customer satisfaction and the quality of delivered results. 
  • You are a strong team player and a good communicator. Sharing the progress of tasks, seeking feedback from your colleagues, and acting as a soundboard, is important to you. 

Jobbeskrivelse

Titel
DTCO Layout R&D Engineer
Arbejdsgiver
Beliggenhed
Kapeldreef 75 Leuven, Belgien
Publiceret
2025-07-02
Ansøgningsfrist
Uspecificeret
Jobtype
Gem job

Jobs from this employer

Viser job i Engelsk, Spansk Skift indstillinger

Om arbejdsgiveren

The combination of our widely acclaimed leadership in microchip technology and profound software and ICT expertise is what makes us unique.

Besøg arbejdsgiverens side

Interessante artikler

...
Bringing Artificial Intelligence Into the Real World Mohamed bin Zayed University of Artificial Intelligence (MBZUAI) 4 min læsning
...
Exposing the Dark Side of Social Media University of Oulu 4 min læsning
...
Six Reasons to Join MBZUAI: Where Research and Innovation Meet Opportunity Mohamed bin Zayed University of Artificial Intelligence (MBZUAI) 4 min læsning
Flere Stories